(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to selectively ion implant multiple collector regions, in an area between a base region, and an underlying subcollector region.
(2) Description of the Prior Art
Bipolar junction transistors feature improved performance, in terms of switching speeds or device frequency, (Ft), compared to metal oxide semiconductor field effect transistors, (MOSFET). The performance of bipolar devices are influenced by many elements, including the base width of the device, as well as junction capacitances. Advances in specific fabrication disciplines, such as ion implantation, has allowed narrow base widths to be realized, thus resulting in a higher Ft, and increased device performance. However to further narrow base widths, a base width xe2x80x9ctailxe2x80x9d, sometimes located at the bottom of the base region, has to minimized. The base width xe2x80x9ctailxe2x80x9d can add unwanted depth to the base width, at the interface of the base width xe2x80x9ctailxe2x80x9d and a lightly doped, underlying collector region. The collector region, usually comprised of a lightly doped epitaxial silicon layer, located overlying a heavily doped, buried layer, of the same conductivity type, is maintained at a low dopant concentration level to minimize capacitance at the collectorxe2x80x94base junction. Thus performance trade-offs exist, in terms of limiting base width via use increased collector dopant concentration, or limiting capacitance via decreasing the dopant level of the collector region.
This invention will describe a process in which selectively implanted collector, (SIC), regions, with a dopant concentration greater than the dopant concentration in the epitaxial collector region, is used truncate the tail of the base region, limiting the base width, while minimizing the increase in capacitance, at the collectorxe2x80x94base junction, resulting from the use of the higher dopant SIC regions. Prior art such as Matthews, in U.S. Pat. No. 5,336,926, describe a bipolar junction transistor, (BJT), in which a SIC type region is formed in the area of the BJT underlying the emitter region, and overlying the lightly doped, epitaxial collector region. This prior art, using only a single SIC region, does limit the tail of the base region, but still leaves a lightly doped, epitaxial collector region, located between overlying SIC region, and the underlying buried collector region. The existence of this lightly doped collector region, featuring high collector resistance, adversely influences BJT performance. This invention will describe a process in which the entire space, between the base region, and the buried collector region, is filled with the higher dopant, SIC regions. This is accomplished via the ion implantation of multiple SIC regions, each obtained at a specific implant energy and dose, to minimize collector resistance, while also minimizing collectorxe2x80x94base capacitance. If a single, SIC ion implantation procedure were used to fill the space between the base and buried collector region, the temperature excursions needed to effectively create the SIC region, would result in unwanted lateral spreading of the SIC region, increasing collectorxe2x80x94base resistance.
It is an object of this invention to fabricate a BJT, featuring a narrow base width, and low collectorxe2x80x94base capacitance.
It is another object of this invention to create multiple SIC regions, self-aligned to an overlying emitter opening, in an oxide layer, in an area located underlying the base region, and overlying the buried collector region.
It is yet another object of this invention to use specific energies, and specific doses, for the multiple SIC regions, to minimize the lateral spreading of the SIC regions.
In accordance with the present invention a method of fabricating a BJT, using multiple SIC regions, to improve BJT performance, is described. A heavily doped, collector region, is formed on a semiconductor substrate, followed by the growth of an epitaxial silicon layer, exhibiting the same conductivity type as, but at a lower dopant concentration than, the buried, heavily doped, collector region. After formation of a silicon oxide layer, a base region, of opposite conductivity type than the collector region, is formed in a top portion of the epitaxial collector region. After deposition of an undoped, thin polysilicon layer on the silicon oxide layer, located on the surface of the base region, a thick photoresist shape is used as a mask to form an opening in the thin polysilicon layer, exposing a portion of the silicon oxide layer, overlying the base region. The same photoresist shape is then used as a mask to allow multiple ion implantation procedures to create multiple SIC regions, in the bottom portion of the epitaxial collector region, completely filling the space between the base region, and the buried collector region. After removal of the silicon oxide layer, exposed in the opening in the photoresist shape, followed by the removal of the photoresist shape, a polysilicon emitter structure is formed, interfacing the portion of the top surface of base region, exposed in the silicon oxide opening. An anneal cycle allows dopant from the polysilicon emitter to diffuse into the top portion of the base region, creating the emitter region of the BJT, while also activating the ion implanted species, in the multiple SIC regions, resulting in a BJT device, comprised of a narrow base region, located directly overlying multiple SIC regions.